10 micron Pitch Wiring and Bump on Substrate Formed by Imprinting Technology to Apply Low Temperature Flip Chip Bonding

The minimum bump pitch in flip-chip bonding is limited by the difference in expansion or shrinkage caused by the CTE mismatch between the chip and the substrate. So, it has been very difficult to achieve a bonding pitch of 35 micron or less in the conventional technology using such as solder. Due to this technical limitation, integration of hetero-chips with a large number of pin count on a substrate is intensively studied using a so-called 2.5D LSI that uses an interposer which stacks chips three-dimensionally using Si through via (TSV). However, the manufacturing technology such as Si interposer and TSV used for this 2.5D LSI is essentially an expensive process. In this study, we will report a narrow-pitch bonding technology based on low-temperature flip-chip bonding using conductive paste as bumps. In this technology, conductive paste is used to simultaneously form wiring and bump with the pitch of 10 micron on the substrate by imprinting method, then non-conductive paste dispensing, followed by flip-chip bonding, and finally curing at 140 degree C in order to enhance the bonding strength and reduce the resistance of the conductive paste. In order to form wiring and bump with the pitch of 10 micron simultaneously on the substrate, the final wiring and bump shape is formed in advance as a master mold, and this is transferred to a replica mold to form an inverted shape. Further, a conductive paste is filled in the concavity of the replica mold, and then transferred to the substrate. In this way, the same wiring and bump structure with the master mold has been successfully reproduced with the conductive paste on the substrate. The wiring is 5 micron wide and 5 micron high and the aspect ratio is 1, the bump is 5 micron in diameter, the height is 5 to 10 micron and the aspect ratio is 1 to 2. These high aspect ratios are very difficult to realize by conventional printing method like screen printing etc. The narrow pitch flip chip bonding technology developed is not only to minimize the effective chip assembly area, but also to make it possible to apply to hetero-chip integration such as processors and memories with a low-cost process.