Binghui Wang, Zhou Shu, Haigang Yang

A 0.9 V wideband SPLL with an adaptive fast‐locking circuit achieving 24.68 µs settling time reduction

  • Electrical and Electronic Engineering
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AbstractA low‐power wideband self‐biased phase‐locked loop (SPLL) is proposed for multi‐protocol SerDes applications in this letter. With the proposed adaptive fast‐locking current circuit (AFLCC) and self‐biased charge pump (CP), the settling time is reduced significantly, and no extra power and jitter contribution. In addition, a start‐up module is adopted to reset the system to an optimal initial operating frequency quickly. The proposed 1‐3‐GHz SPLL, fabricated in TSMC 28‐nm CMOS process, occupies a compact 0.028 mm2 area. It achieves a roughly constant settling time of 5 μs over all frequencies and division ratios range. Only 0.96 mW is consumed at 1 GHz frequency.

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