DOI: 10.4071/001c.116707 ISSN: 2380-4505

Adaptive High Density RDL Technologies for Panel Level Packaging

Lars Böttcher

The scaling from wafer-level to panel-

level is expected to be the next evolution of fan-out (FO) packaging.

However, there is still a technical gap between wafer front-end technologies and the PCB infrastructure. One major technological challenge to close this

gap is to lower the structure size of

lines and spaces (L/S) significantly.

While L/S is going smaller, panel size

is going up to 600 x 600 mm².

This paper will show the development

of 5µm L/S RDL routing density and

chips with 50µm bump pitch. Here, the

6x6 mm² dies are symmetrically

embedded into an organic laminate

matrix. A PCB core (100µm thickness)

with very low coefficient of thermal

expansion (CTE) containing laser cut

cavities is used, acting as a frame

layer. Besides mechanical and handling stability, the usage of such a frame

offers the advantage of pre-integrating additional features like local fiducials, through vias or power

lines by conventional PCB processes.

Within that frame, the dies are embedded by lamination of an organic build-up film with 25µm thickness

equal to bump height. The chip contacts are then opened without the need of any micro via formation. Here

a strong focus is set on RIE etching

of the polymer material.

Highly accurate measurement of the

real die position is essential for the

following processing. The formation of

the redistribution layer (RDL) is done

in a semi-additive process (SAP)

utilizing sputtering technique and

direct imaging (LDI). To achieve the

fine pitch demands, an adaptive

imaging process is applied. Therefore,

a newly developed LDI machine is used

to write structures in a 7µm photoresist. This exposure also

combines the measurement data of the real die position and the adaption of

the exposure artwork, in order to achieve highest registration quality.

The innovative developments of this

PLP demonstrator will be discussed in

detail.

The next step in development will

target to achieve 2µm L/S structure

size. First steps toward this goal

will be addressed briefly.

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