AFHRE: An Accurate and Fast Hardware Resources Estimation Method for Convolutional Accelerator with Systolic Array Structure on FPGA

FPGA-based convolutional accelerators have been widely used in image recognition scenarios. Many convolutional accelerators utilize the systolic array structure to enhance parallelism. Developing a method to efficiently estimate the utilized hardware resources of an FPGA for such a structure would be helpful in improving the speed of achieving an optimal systolic array structure with the best performance on a given FPGA device. Currently, most estimations of work have either focused on the evaluation of hardware resources for general structures or have not adequately assessed hardware resources specifically for systolic arrays. To reduce estimation latency, this paper proposes an Accurate and Fast Hardware Resources Estimation method (AFHRE) that addresses these shortcomings by analyzing the structure of systolic arrays and utilizing mathematical formulas to describe their characteristics. Experiments show that the DSP resource occupancy estimated by AFHRE is fully consistent with that by Vivado HLS. The error rates of other three types of hardware resources (BRAM, LUT, and FF) are within 11%. In addition, the speed of resource estimation using this method is 40X to 610X faster than that of Vivado HLS. AFHRE can serve as a preprocessing step for Vivado HLS, achieving some optimal or sub-optimal solutions systolic array parameters much faster than original simulation manners of Vivado HLS.