An ultrahigh input impedance low noise analog front‐end design for epilepsy brain recording system

Summary

This paper presents an ultrahigh input impedance, low noise, and wide bandwidth four‐channels analog front‐end (AFE) for low‐power neural recording systems. To achieve high input impedance, the buffer channels are placed between the electrodes and the main amplifier stage of the AFE. The buffer is designed with low noise and low power consumption to obtain high input impedance of overall AFE while maintaining low input‐referred noise and low power consumption. A chopper capacitively coupled chopper instrumentation amplifier (CCIA) is placed after the buffer as the main amplifier stage of the AFE to improve the common mode rejection ratio (CMRR) and the input‐referred noise of the overall AFE design. A new chopper stabilization control technique is proposed and used in the CCIA stage to reduce the charge injection and clock feedthrough and consequently the high‐frequency ripple of the AFE output signal. A programmable gain amplifier (PGA) is designed as the third stage to adjust the overall gain of the AFE. Benefiting from PGA, the AFE can adapt its gain with both action potential and local field potential signals. To reduce the number of the electrode to be implanted and reduce the impedance mismatch that causes the degradation on overall CMRR performance, two AFE channels shared a reference electrode followed by a reference buffer. The proposed AFE is designed and simulated using a standard 180 nm CMOS process and operates in a wide frequency band of 2.1 to 2500 Hz with low input‐referred noise of 1.6 μVrms and a CMRR over 80 dB at 2.1 Hz. The total power consumption is lower than 4.3 μW per channel. With the proposed structure of AFE, the input impedance is 35 GΩ @ 21 Hz and the minimum impedance over operational bandwidth is 75 MΩ @ 2.5 kHz.