In digital audio systems, filters and equalizers are essential modules for audio improvement at the input and output stages. Due to their computational complexity, most audio tasks are processed with digital signal processors. Due to the fact that latency in audio systems is a critical specification and audio trends require higher sample rates, noise canceling, and bigger data sizes, having an independent high-resolution equalizer would reduce the computational power needed for audio systems. This research had the goal of designing and implementing a hardware architecture for a configurable filter bank based on finite impulse response (FIR) filters and a noise-cancellation stage with an inter-integrated circuit (I2C) communication interface, which allows the filter configuration. The system was implemented as a standalone integrated circuit (IC) for which its inputs were the inter-IC sound (I2S) bus control signals. The digital audio system was optimized to perform one-cycle convolutional operations by implementing a vector–vector arithmetic logic unit. Furthermore, this applied research provides the register transfer level description and the functional verification of the digital design, the system-on-chip (SoC) implementation in TSMC 180 nm technology, and the post-silicon validation with a printed circuit board for testing the output digital signals of the system.

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