Chip Package Bumping on Wafer-Level for RDL First Fan-Out Wafers

Fan-out wafer-level packaging (FOWLP) is one of the most attractive advanced packaging trends in microelectronics since it allows an improved form factor with reduced package volume and package thickness. Moving to an era of System-in-Package (SiP) and heterogeneous integration, FOWLP is an increasingly important packaging approach. FOWLP also enables better thermal packaging performance with a shorter heat dissipation path from the die to the printed circuit board (PCB). FOWLP combines multiple chips from heterogeneous processes into a compact package, thereby reducing the footprint. Chips (also known as known good dies or KGD) are embedded in an epoxy molded compound (EMC) and then a metal redistribution layer (RDL) establishes the connections within the package without any need of Through Silicon Vias (TSVs) or a laminate package substrate. In an RDL first approach, RDL layers are built-up on a carrier wafer and known good dies are attached to the RDL followed by the molding process and solder bumping. Wafer handling challenges appear after epoxy molding that lead to warpage of the molded wafer due to the coefficient of thermal expansion (CTE) mismatch between silicon (Si) and the mold compound.

In this work, a solder bumping process of RDL first fan-out molded wafers are evaluated at the wafer level and the handling challenges faced during these evaluations are explained. Bumping machine capability for handling warped wafers shows successful handling of wafer warpage of ~3mm for dummy wafers. The bumping process evaluation was carried out on real wafers with warpage <1mm. Handling real wafers during the bumping process is critical since the epoxy molded wafers are like paper. The solder bumping process was carried out as a ball drop on flux process in which solder balls of a lead-free solder alloy, tin-silver-copper (Sn-Ag-Cu), are placed from a reservoir through a stencil onto an already flux-printed pad surface; a subsequent reflow step is needed to confirm good adhesive bonding of the balls to the pads.

Performing a reflow process on molded wafers is quite challenging due to the mechanical stress generated at the high temperature used for reflow, which may influence the performance of the device. Mechanical stress and deformation of the molded wafer is observed due to the mold compound shrinkage at high temperature and thermal expansion differences between the chip and mold compound. Again, processing FOWLP wafers during solder reflow to a peak temperature of ~250°C is critical due to their thermal fragility. A low temperature solder process can be tried using low melting temperature solder alloys like indium-tin (In-Sn) or indium-bismuth (In-Bi), but this limits many operations on the device. Reflow processes for the reconstituted wafers in this study are performed at a peak temperature of 245°C for a few seconds and a total reflow cycle time of 5 minutes. Wafers were glued to Si dummy wafers for better handling during the reflow process and specially designed transport plates were used for transporting the wafers through different stations.