Die-to-Die Interconnect Design and Simulation for 2.3D Organic Interposer Package

For high performance compute (HPC) applications, the disaggregation of large silicon SOCs into smaller silicon elements has been shown to have benefits in both silicon manufacturing yields and design scalability. The silicon elements are re-aggregated using advanced packaging technologies with high bandwidth die-to-die connections. This investigation uses a parallel multi-channel I/O interface to maintain a high data rate with minimal errors. Advanced packaging offers different physical medium options ranging from organic substrates (FCBGA) to silicon interposers and bridges (2.5D). This study focuses on organic interposers that use high-density fan-out copper redistribution layers (RDL) to interconnect adjacent ICs and to the underlying substrate. This ‘2.3D’ interposer technology is a sequentially manufactured stack of electroplated Copper layers and Polyimide dielectric layers. In this study several die-to-die 2.3D interposer designs with various RDL topologies were considered. In order to pass the electrical performance and ultimately ensure signal integrity, designers must pay careful attention to routing and grounding scenarios. The results will show that a staggered GSG approach passes the chosen signal integrity analysis by using 3D EM tools and circuit simulators.