Performance Evaluation of an Efficient Dual Stage Compressor Using 32 nm CNTFET Technology for High Speed and Low Power Digital Applications

In the pursuit of heightened computational prowess and operational efficiency, the adoption of approximation techniques stands as a promising avenue to alleviate the computational burdens on processor units. Striving for accelerated operational speeds often demands extensive parallel processing, which, in turn, escalates hardware and power requisites, inevitably entailing a trade-off with system latency. Embracing a reduction in system precision and reliability offers the potential to craft systems that are both energy-efficient and space-conscious. Approximate computing emerges as a compelling approach to strike a balance among latency, hardware footprint, and power consumption, catering to systems where expedited computation and diminished power consumption reign supreme, even at the expense of absolute accuracy. Simplifying system design by curtailing complexity, latency, and power consumption is central to the efficacy of these methods. This paper delves into the development of power-efficient circuits for approximate multiplication through a novel lens, employing a modified 4:2 compressor architecture. Unlike preceding designs, this research introduces a fresh approach by integrating an error recovery module with a refined version of the conventional 4:2 compressor concept. Despite experiencing slightly elevated power and delay consumption at the same precision level, the proposed design showcases enhanced accuracy, reduced hardware requirements, and diminished power consumption compared to prior 4:2 compressor-based approximation multiplication techniques, even with the incorporation of an error recovery mechanism. Moreover, the investigation extends to the comparison between 130 nm CMOS technology and 32 nm CNTFET technology. The analysis reveals that the utilization of 32 nm CNTFET technology demonstrates superior efficiency over traditional MOSFET technology, further enhancing the overall performance and energy efficiency of the proposed designs. The performance and efficiency of these designs, implemented utilizing 130 nm CMOS technology, have been meticulously assessed and extrapolated across diverse metrics encompassing area, delay, power, and Power Delay Product (PDP). This study underscores the potential advantages of leveraging a specialized 4:2 compressor design, distinguished by its superior speed, area efficiency, and reduced power consumption, particularly in multiplier applications requiring high-speed operations.